RWE=0, ACKTWE=0
SCL Stretch Control Register
| ACKTWE | Acknowledge Transmission Wait Enable 0 (0): NTST.RDBFF0 is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) 1 (1): NTST.RDBFF0 is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) Low-hold is released by writing a value to the ACKCTL.ACKT bit. |
| RWE | Receive Wait Enable 0 (0): No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) 1 (1): WAIT (The period between ninth clock cycle and first clock cycle is held low.) Low-hold is released by reading NTDTBP0. |